Former AMD Engineer: The Hardware World Deeply Exceeds Software Tourists' Imagination
Former AMD engineer Hemant Mohapatra shared his career experience: during his first week on the job, he witnessed a manager manually reverse-engineering Intel's latest chip's NAND and XOR logic gates using an electron microscope. At that time, after AMD64 took the lead, Intel interrupted the IP sharing protocol, forcing the team to manually parse the transistor layout at the physical layer.
He responded to the Dwarkesh podcast, emphasizing that professionals in the GPU, CPU, networking, and data center fields possess unparalleled advantages—this field is filled with history, heartbreak, failures, and espionage stories, far from what "tourists" can quickly master.
Source: Public Information
ABAB AI Insight
Mohapatra's story reveals the "physical barriers" inherent in the hardware industry: software can be abstracted and iterated, while hardware is anchored in atomic-level processes and historical entanglements. The interruption of Intel-AMD's IP sharing forced reverse engineering from contracts to manual dissection under a microscope, reflecting not only technological competition but also a microcosm of industrial espionage and patent wars.
This narrative mirrors the fracturing of the Silicon Valley paradigm: the influx of "software tourists" with the AI wave overlooks the accumulated complexity at the infrastructure level. The history of data centers and chip design encompasses 50 years of failed iterations and supply chain games, with only "natives" mastering its tacit knowledge. This asymmetry determines the distribution of control in the AI hardware supply chain.
In the long-term structure, it foreshadows the return of "hardware sovereignty." Software agents can rewrite the application layer, but the physical layer still requires human endurance and craftsmanship inheritance. Mohapatra's experience reminds us that the outcome of the next round of computing competition will be decided at the transistor level rather than at the token level.